The present invention relates to a memory access control device which is for controlling access to a memory device. The memory device comprises a plurality of memory modules, each of which comprises a predetermined number of memory banks.
A memory access control device of the type described, generally comprises an address signal processing circuit, a first bank address signal holding circuit, a second bank address signal holding circuit, a first bank access signal holding circuit, a second bank access signal holding circuit, a first bank access checking circuit, a second bank access checking circuit, an access judging circuit, a shift signal supply circuit, and an access signal output control circuit.
The address signal processing circuit is supplied with a first input address signal comprising a first module address portion, a first bank address portion, and a first element address portion and a second input address signal comprising a second module address portion, a second bank address portion, and a second element address portion and processes the first and the second bank address portions into first and second bank address signals and produces the first and the second input address signals as first and second address signals as they are.
The address signal processing circuit is supplied with the first and the second input address signals from first and second processors.
The first and the second input address signals are identical with the first and the second address signals. The first bank address signal holding circuit is connected to the address signal processing circuit and holds the first bank address signal as a first bank address held signal. The second bank address signal holding circuit is connected to the address signal processing circuit and holds the second bank address signal as a second bank address held signal.
The first bank access signal holding circuit is connected to the first bank address signal holding circuit, corresponds to one of the memory modules, and holds a first bank access held signal. The second bank access signal holding circuit is connected to the second bank address signal holding circuit, corresponds to the above-mentioned memory module, and holds a second bank access held signal.
The first bank access checking circuit is connected to the address signal processing circuit and the first bank access signal holding circuit, corresponds to a different memory module, and checks the first bank address signal and the first bank access held signal to produce a first bank coincidence signal when the first bank address signal and the first bank access held signal coincide with each other. The second bank access checking circuit is connected to the address signal processing circuit and the second bank access signal holding circuit, corresponds to the different one of the memory modules, and checks the second bank address signal and the second bank access held signal to produce a second bank coincidence signal when the second bank address signal and the second bank address held signal coincide with each other.
The access judging circuit is connected to the module checking circuit and the first and the second bank access checking circuits and alternately produces a first inhibit signal and a second inhibit signal when supplied with the module coincidence signal. The access judging circuit produces the first inhibit signal when supplied with the first bank coincidence signal. The access judging circuit produces the second inhibit signal when supplied with the second bank coincidence signal. The access judging circuit produces first and second shift signals when the first and second inhibit signals are not produced, respectively.
The shift signal supply circuit is connected to the access judging circuit and the first and the second bank address signal holding circuits and uses the first and the second shift signals in transferring the first bank address held signal to the first bank access signal holding circuit as the first bank access held signal and in transferring the second bank address held signal to the second bank access signal holding circuit as the second bank access held signal.
The access signal output control circuit is connected to the above-mentioned plurality of memory modules, the address signal processing circuit, and the access judging circuit. The access signal output control circuit specifies by the first address signal, as a first specified memory module and a first specified memory bank, a particular memory module of the and a particular memory bank of the predetermined number of memory banks in the particular memory module. The access signal output control circuit sends the first element address portion to the first specified memory bank of the first specified memory module when the access signal output control circuit is supplied with the first address signal and when the access judging circuit does not produce the first inhibit signal. The access signal output control circuit specifies by the second address signal, as a second specified memory bank module and a second specified memory bank, a specific memory module of the number of memory modules and a specific memory bank of the predetermined number of memory banks in the specific memory module. The access signal output control circuit sends the second element address portion to the second memory bank of the second specified memory module when the access signal output control circuit is supplied with the second address signal and when the access judging circuit does not produce the second inhibit signal. The memory access control device can prevent the first and the second processors from accessing the same memory module at the same.
In the memory access control device thus far described, the first bank access checking circuit corresponds to only one of the memory modules and the second bank access checking circuit corresponds to the above-mentioned one of the memory modules. Thus, the memory access control device has the same number of memory modules and the same number of bank access checking circuits. Consequently, the memory access control device must comprise a large amount of hardware particularly when the memory modules are large in number.